Infineon

Senior Staff Engineer - AMS Verifi...

Infineon
Bangalore
500,000-600,000 Year
9 - 12 Years
Posted:
30+ days ago
Full time
Applicants:
0
Job Description

As a AMS Verification Engineer one should have working experience with AMS Verification on multiple SOC s or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment.


  • Ability to lead MSV and/or DV verifications.
  • Involved in verification for IPs .
  • Handling project dynamics on scope, schedule and effort - coming up with alternative verification plans, Mentoring Junior engineer.
  • Test plan preparation as per the dynamics of product specifications.
  • Behavioral modeling: Verilog, real or SV-RNM .
  • Dealing challenges with AMS methodologies of Cadence irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS.
  • Testcase Debug & proposing new scenarios.
  • Ability to strategize optimization of simulation bench for simulation time.

Your Profile

You are best equipped for this task if you have:

  • Bachelors with 9+ years or Masters with 8+ years of experience.
  • Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage.
  • HDL/HVL Verilog Verilog-ams SV/UVM added advantage.
  • Tools: Cadence Xcelium spectre Synopsys XA-VCS Mentor Eldo ADMS .
  • Automation: Perl/python/shell.
  • Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements.
  • Ability to drive projects and debug independently

Role: Design Verification Engineer

Industry Type: Electronic Components / Semiconductors

Department: Engineering - Hardware & Networks

Employment Type: Full Time, Permanent

Role Category: Hardware

Education

UG: Any Graduate

PG: Any Postgraduate

Job Requirment
Role:
Senior Staff Engineer - AMS Verification
Industry:
Department:
Engineering
Employment Type:
Full time
Education
Graduate
Skills
Automation
Analog Design
Python
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