• Developing and reviewing verification plans for SERDES/PHY/Controller IPs.
• Creating and maintaining verification environments, with a preference for UVM.
• Conducting RTL, GLS, and co-simulations to ensure comprehensive coverage closure.
• Delivering high-quality RTL and simulation models to customers.
• Using third-party VIP for protocol verification and simulation bring-up of protocol subsystems.
• Supporting customers with IP integration, silicon bring-up, and debugging issues.
• Demonstrating Testchip+FPGA system demos to customers and at conferences.

Role: Design Verification Engineer

Industry Type: IT Services & Consulting

Department: Engineering - Hardware & Networks

Employment Type: Full Time, Permanent

Role Category: Hardware

Education

UG: Any Graduate

PG: Any Postgraduate

About the company

Synopsys delivers trusted and comprehensive silicon to systems design solutions, from electronic design automation to silicon IP and system verification and validation. We partner closely with semiconductor and systems customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.For over 30 years, Synopsys has fostered a culture of growth, innovation, and inclusivity. Our diverse learning opportunities and rotational programs empower team members to thrive. Recognized as a leader in workplace inclusivity, we’ve been honored as one of the Best Companies for Diversity and a Great Place to Work in 14 countries.