Hello Connections

Greetings from Interex semiconductor 

hashtag#immediatehiring hashtag#bengaluru

Role:hashtag#analoglayoutdesignengineer

Experience: 5+years 

Location: hashtag#bengaluru

Notice period: Immediate Joiner

JD:

Role and Responsibilities

* Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support.

* Perform layout verification like LVS/DRC/Antenna, quality check and documentation.

* Responsible for on-time delivery of block-level layouts with acceptable quality.

* Contribute to effective project-management.

* Effectively communicating with engineering teams in the India, US, and Japan to assure the success of the layout project.

Qualification/Requirements

* 5-7 year experience in analog/custom layout design in advanced CMOS process.

* Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.

* Should have hands on experience of Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc.,

* Good understanding of Analog Layout fundamentals (e.g. Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc.)

* Understanding layout effects on the circuit such as speed, capacitance, power and area etc.,

* Ability to understand design constraints and implement high-quality layouts.

* Excellent command and problem-solving skills in Physical layout verification.

* Good understanding of basic active and passive devices such as R,L, C and MOSFETs

* Scripting and automation experience is good to have but not mandatory.

* Excellent verbal and written communication skills.