Hello Connections

Greetings from Interex semiconductor hashtag#immediatehiring hashtag#hyderabad

Role:hashtag#standardcellslayout

Experience: 1+years 

Location: hashtag#hyderabad

Notice period: Immediate Joiner

JD:

Doing STD cells characterization work (max up to 40% of time) , Static timing analysis (60%)

•Able to characterize basic STD Cells

•Writing ARC for STD cell char (using primeLib , Silicon smart) lib QA check

•Circuit understanding block wise , Full chip level

•Static timing Analysis of DRAM block wise , top level analysis , cell level analysis

•Writing constraints , analyzing the STA reports

•Reporting violations to Design team , ownership for closure

•Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions

•Performing verification processes with modeling and simulation using industry standard simulators

•Contributing to cross group communication to work towards standardization and group success

•Driving innovation into the future Memory generations within a dynamic work environment.